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| 1. general description the pcf8523 is a cmos 1 real-time clock (rtc) and calendar optimized for low power consumption. data is transferred serially via an i 2 c-bus with a maximum data rate of 1000 kbit/s. alarm and timer functions are av ailable with the possibility to generate a wake-up signal on an interrupt pin. an offset register allows fine-tun ing of the clock. the pcf8523 has a backup battery switch-over circuit, which detects power failures and automatically switches to the battery supply when a power failure occurs. 2. features and benefits ? provides year, month, day, weekday, hours, minutes, and seconds based on a 32.768 khz quartz crystal ? resolution: seconds to years ? clock operating voltage: 1.0 v to 5.5 v ? low backup current: typical 150 na at v dd = 3.0 v and t amb =25 ? c ? 2 line bidirectional 1 mhz fast-mode plus (fm+) i 2 c interface, read d1h, write d0h 2 ? battery backup input pin and switch-over circuit ? freely programmable ti mer and alarm with interrupt capability ? selectable integrated oscilla tor load capacitors for c l =7pf or c l = 12.5 pf ? internal power-on reset (por) ? open-drain interrupt or clock output pins ? programmable offset register for frequency adjustment 3. applications ? time keeping application ? battery powered devices ? metering pcf8523 real-time clock (rtc) and calendar rev. 4 ? 5 july 2012 product data sheet 1. the definition of the abbreviations and acronyms used in this data sheet can be found in section 20 . 2. devices with other i 2 c-bus slave addresses can be produced on request.
pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 2 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 4. ordering information 4.1 ordering options [1] bump hardness see table 53 . 5. marking table 1. ordering information type number package name description version pcf8523t so8 plastic small outline package; 8 leads; body width 3.9 mm sot96-1 pcf8523tk hvson8 plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 4 ? 4 ? 0.85 mm sot909-1 pcf8523ts tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 pcf8523u bare die 12 bumps (6-6) pcf8523u table 2. ordering options type number ic revision sales item (12nc) bump type delivery form pcf8523t/1 1 935293581118 - tape and reel, 13 inch pcf8523tk/1 1 935293573118 - tape and reel, 13 inch pcf8523ts/1 1 935291196112 - tube 935291196118 - tape and reel, 13 inch pcf8523u/12aa/1 1 935293887005 soft gold bumps [1] sawn wafer on film frame carrier (ffc) table 3. pcf8523u wafer information type number wafer thickness wafer diameter ffc for wafer size marking of bad die pcf8523u/12aa/1 200 ? m 6 inch 8 inch wafer mapping table 4. marking codes type number marking code pcf8523t/1 8523t pcf8523tk/1 8523 pcf8523ts/1 8523ts pcf8523u/12aa/1 pc8523-1 pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 3 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 6. block diagram fig 1. block diagram of pcf8523 013aaa305 pcf8523 oscillator 32.768 khz divider clock out interrupt int2 power-on reset i 2 c-bus interface osci scl sda osco v bat v dd v ss c osci c osco battery backup switch-over circutry clock calibration offset system control real-time clock alarm timer & int1/clkout clkout pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 4 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 7. pinning information 7.1 pinning top view. for mechanical details, see figure 37 on page 54 . fig 2. pin configuration for so8 (pcf8523t) for mechanical details, see figure 38 on page 55 . fig 3. pin configuration for hvson8 (pcf8523tk) top view. for mechanical details, see figure 39 on page 56 . fig 4. pin configuration for tssop14 (pcf8523ts) pcf8523t osci v dd osco int1/clkout v bat scl v ss sda 013aaa306 1 2 3 4 6 5 8 7 013aaa308 sda v ss scl v bat int1/clkout osco v dd osci transparent top view 5 4 6 3 7 2 8 1 terminal 1 index area pcf8523tk pcf8523ts osci v dd osco int1/clkout n.c. n.c. v bat scl v ss sda n.c. n.c. int2 clkout 013aaa307 1 2 3 4 5 6 7 8 10 9 12 11 14 13 pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 5 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 7.2 pin description [1] wire length between quartz and package should be minimized. [2] for manufacturing tests only; do not connect it and do not use it. [3] the die paddle (exposed pad) is connected to v ss and should be electrically isolated. [4] the substrate (rear side of the die) is connected to v ss and should be electrically isolated. viewed from active side. for mechanical details, see figure 40 on page 57 . fig 5. pin configuration for pcf8523u 013aaa317 2 1 pcf8523u 3 4 5 6 7 12 11 10 9 8 v dd osci osco v bat v ss int2 n.c. clkout sda scl n.c. int1/clkout table 5. pin description symbol pin type description so8 (pcf8523t) hvson8 (pcf8523tk) tssop14 (pcf8523ts) pcf8523u osci 1 1 1 2 input oscillator input; high-impedance node [1] osco 2 2 2 3 output oscillator output; high-impedance node [1] n.c. - - 3, 6, 9, 12 [2] 6 and 11 [2] - not connected; do not connect and do not use it as feed through v bat 3 3 4 4 supply battery supply voltage v ss 44 [3] 55 [4] supply ground supply voltage int2 - - 7 7 output interrupt 2 (open-drain, active low) clkout - - 8 8 output clock output (open-drain) sda 5 5 10 9 input/output serial data input/output scl 6 6 11 10 input serial clock input int1 /clkout 7 7 13 12 output interrupt 1/clock output (open-drain) v dd 8 8 14 1 supply supply voltage pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 6 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8. functional description the pcf8523 contains: ? 20 8-bit registers with an auto-incrementing address register ? an on-chip 32.768 khz oscillator with two integrated load capacitors ? a frequency divider, which provides the source clock for the real-time clock (rtc) ? a programmable clock output ? a 1 mbit/s i 2 c-bus interface ? an offset register, which allo ws fine-tuning of the clock all 20 registers are designed as addressable 8-bit registers although not all bits are implemented. ? the first three registers (memory address 00h, 01h, and 02h) are used as control and status registers ? the addresses 03h through 09h are used as c ounters for the cloc k function (seconds up to years) ? addresses 0ah through 0dh define the alarm condition ? address 0eh defines the offset calibration ? address 0fh defines the clock-out mode and the addresses 10h and 12h the timer mode ? addresses 11h and 13h are used for the timers the registers seconds, minu tes, hours, days, weekdays, months, and years are all coded in binary coded decimal (bcd) format. other registers are either bit-wise or standard binary. when one of the rtc registers is read, the contents of all counters are frozen. therefore, faulty reading of the cl ock and calendar during a carry condition is prevented. the pcf8523 has a battery backup input pin a nd battery switch-over circuit. the battery switch-over circuit monitors the main power supply and switches automatically to the backup battery when a power failure condit ion is detected. accurate timekeeping is maintained even when the main power supply is interrupted. a battery low detection circuit monitors the stat us of the battery. when the battery voltage goes below a certain threshold value, a flag is set to indicate that the battery must be replaced soon. this ensures the integrity of the data during periods of battery backup. pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 7 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.1 registers overview the 20 registers of the pcf8523 are auto-incrementing after each read or write data byte up to register 13h. after register 13h, the auto-incrementing will wr ap around to address 00h (see figure 6 ). fig 6. auto-incrementing of the registers 013aaa309 address register 00h auto-increment wrap around 01h 02h 03h ... 11h 12h 13h table 6. registers overview bit positions labeled as - are not implemented and will return a 0 when read. bit t must always be written with logic 0. address register name bit 7 6 5 4 3 2 1 0 control registers 00h control_1 cap_sel t stop sr 12_24 sie aie cie 01h control_2 wtaf ctaf ctbf sf af wtaie ctaie ctbie 02h control_3 pm[2:0] - bsf blf bsie blie time and date registers 03h seconds os seconds (0 to 59) 04h minutes - minutes (0 to 59) 05h hours - - ampm hours (1 to 12 in 12 hour mode) hours (0 to 23 in 24 hour mode) 06h days - - days (1 to 31) 07h weekdays - - - - - weekdays (0 to 6) 08h months - - - months (1 to 12) 09h years years (0 to 99) alarm registers 0ah minute_alarm ae_m minute_alarm (0 to 59) 0bh hour_alarm ae_h - ampm hour_alarm (1 to 12 in 12 hour mode) - hour_alarm (0 to 23 in 24 hour mode) 0ch day_alarm ae_d - day_alarm (1 to 31) 0dh weekday_alarm ae_w - - - - weekday_alarm (0 to 6) offset register 0eh offset mode offset[6:0] pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 8 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar clockout and timer registers 0fh tmr_clkout_ctrl tam tbm cof[2:0] tac[1:0] tbc 10h tmr_a_freq_ctrl - - - - - taq[2:0] 11h tmr_a_reg timer_a_value[7:0] 12h tmr_b_freq_ctrl - tbw[2:0] - tbq[2:0] 13h tmr_b_reg timer_b_value[7:0] table 6. registers overview ?continued bit positions labeled as - are not implemented and will return a 0 when read. bit t must always be written with logic 0. address register name bit 7 6 5 4 3 2 1 0 pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 9 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.2 control and status registers 8.2.1 register control_1 [1] default value. [2] must always be written with logic 0. [3] for a software reset, 01011000 (58h) must be sent to register control_1 (see section 8.3 ). bit sr always returns 0 when read. table 7. control_1 - control and status re gister 1 (address 00h) bit description bit symbol value description 7 cap_sel internal oscillator capacitor selection for quartz crystals with a corresponding load capacitance 0 [1] 7pf 112.5pf 6t 0 [1] [2] unused 5stop 0 [1] rtc time circuits running 1 rtc time circuits frozen; rtc divider chain flip-flops are asynchronously set logic 0; clkout at 32.768 khz, 16.384 khz, or 8.192 khz is still available 4sr 0 [1] [3] no software reset 1 initiate software reset 3 12_24 0 [1] 24 hour mode is selected 1 12 hour mode is selected 2sie 0 [1] second interrupt disabled 1 second interrupt enabled 1aie 0 [1] alarm interrupt disabled 1 alarm interrupt enabled 0cie 0 [1] no correction interrupt generated 1 interrupt pulses ar e generated at every correction cycle (see section 8.8 ) pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 10 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.2.2 register control_2 [1] default value. table 8. control_2 - control and status re gister 2 (address 01h) bit description bit symbol value description 7wtaf 0 [1] no watchdog timer a interrupt generated 1 flag set when watchdog timer a interrupt generated; flag is read-only and cleared by reading register control_2 6ctaf 0 [1] no countdown timer a interrupt generated 1 flag set when countdown timer a interrupt generated; flag must be cleared to clear interrupt 5ctbf 0 [1] no countdown timer b interrupt generated 1 flag set when countdown timer b interrupt generated; flag must be cleared to clear interrupt 4sf 0 [1] no second interrupt generated 1 flag set when second interrupt generated; flag must be cleared to clear interrupt 3af 0 [1] no alarm interrupt generated 1 flag set when alarm triggered; flag must be cleared to clear interrupt 2wtaie 0 [1] watchdog timer a interrupt is disabled 1 watchdog timer a interrupt is enabled 1ctaie 0 [1] countdown timer a interrupt is disabled 1 countdown timer a interrupt is enabled 0ctbie 0 [1] countdown timer b interrupt is disabled 1 countdown timer b interrupt is enabled pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 11 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.2.3 register control_3 [1] default value is 111. [2] default value. table 9. control_3 - control and status re gister 3 (address 02h) bit description bit symbol value description 7 to 5 pm[2:0] see ta b l e 11 [1] battery switch-over and battery low detection control 4 - - unused 3 bsf 0 [2] no battery switch-over interrupt generated 1 flag set when battery s witch-over occurs; flag must be cleared to clear interrupt 2blf 0 [2] battery status ok 1 battery status low; flag is read-only 1 bsie 0 [2] no interrupt generated from battery switch-over flag, bsf 1 interrupt generated when bsf is set 0blie 0 [2] no interrupt generated from battery low flag, blf 1 interrupt generated when blf is set pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 12 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.3 reset a reset is automatically generated at power-o n. a reset can also be initiated with the software reset command. software reset command means setting bits 6, 4, and 3 in register control_1 (00h) logic 1 and all other bits logic 0 by sending the bit sequence 01011000 (58h), see figure 7 . fig 7. software reset command s11010000a0000000 0a01011000a p/s sda scl internal reset signal slave address byte address 00h software reset 58h r/w 013aaa320 table 10. register reset values bits labeled x are undefined at power-on and unchanged by subsequent resets. bits labeled - are not implemented. address register name bit 7 6 5 4 3 2 1 0 00h control_1 0 0 0 0 0 0 0 0 01h control_2 0 0 0 0 0 0 0 0 02h control_3 1 1 1 - 0 0 0 0 03h seconds 1 xxxxxxx 04h minutes - xxxxxxx 05h hours - - xxxxxx 06h days - - xxxxxx 07hweekdays -----xxx 08h months - - - xxxxx 09h years xxxxxxxx 0ah minute_alarm 1 xxxxxxx 0bh hour_alarm 1 - xxxxxx 0ch day_alarm 1 - xxxxxx 0dhweekday_alarm1----xxx 0ehoffset 00000000 0fh tmr_clkout_ctrl00000000 10h tmr_a_freq_ctrl -----111 11h tmr_a_reg xxxxxxxx 12h tmr_b_freq_ctrl - 0 0 0 - 1 1 1 13h tmr_b_reg xxxxxxxx pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 13 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar after reset, the followin g mode is entered: ? 32.768 khz clkout active ? 24 hour mode is selected ? register offset is set logic 0 ? no alarms set ? timers disabled ? no interrupts enabled ? battery switch-over is disabled ? battery low detection is disabled ? 7 pf of internal oscilla tor capacitor selected 8.4 interrupt function active low interrupt signals are available at pin int1 /clkout and int2 . pin int1 /clkout has both functions of int1 and clkout combined. int1 interrupt output may be sourced from different places: ? second timer ? timer a ? timer b ? alarm ? battery switch-over ? battery low detection ? clock offset correction pulse int2 interrupt output is sourced only from timer b: the control bit tam (register tmr_clkout_ctrl) is used to configure whether the interrupts generated from the second interrupt timer and timer a are pulsed signals or a permanently active signal. the control bit tb m (register tmr_clkout _ctrl) is used to configure whether the interrupt generated from timer b is a pulsed signal or a permanently active signal. all the other interrupt sources generate a permanently active interrupt signal, which follows the status of the corresponding flags. ? the flags sf, ctaf, ctbf, af, and bsf can be cleared by using the interface ? wtaf is read only. reading of the register control_2 (01h) automatically resets wtaf (wtaf = 0) and clears the interrupt ? the flag blf is read only. it is cleared automatically from the battery low detection circuit when the battery is replaced pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 14 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar when sie, ctaie, wtaie, ctbie, aie, cie, bsie, blie, and clock-out are disabled, then int1 remains high-impedance. when ctbie is disabled, then int2 remains high-impedance. fig 8. interrupt block diagram blf: battery low flag set set battery low flag, blf to interface: read blf blie 013aaa330 from battery low detection circuit: clear blf clear bsf: battery flag set set battery flag, bsf to interface: read bsf bsie from interface: clear bsf clear pulse generator 5 set offset circuit: add/subtract pulse cie from interface: clear cie clear af: alarm flag set set alarm flag, af to interface: read af aie from interface: clear af clear wtaf: watch dog timer flag set watchdog counter a to interface: read wtaf mcu loading watchdog counter or reading wtaf clear ctaf: countdown timer a flag set countdown counter a to interface: read ctaf ctaie int1 0 1 from interface: clear ctaf clear pulse generator 2 trigger clear sf: second flag set seconds counter to interface: read sf sie 0 1 from interface: clear sf clear sie pulse generator 1 trigger clear tam tam clkout int1/clkout enable tac = 01 enable tac = 10 pulse generator 3 trigger clear wtaie 0 1 tam ctbf: countdown timer b flag set countdown counter b to interface: read ctbf ctbie 0 1 from interface: clear ctbf clear pulse generator 4 trigger clear tbm enable tbc = 1 int2 pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 15 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.5 power management functions the pcf8523 has two power supply pins: ? v dd - the main power supply input pin ? v bat - the battery backup input pin the pcf8523 has two power management functions implemented: ? battery switch-over function ? battery low detection function the power management functions are controlled by the control bits pm[2:0] in register control_3 (02h): [1] when the battery switch-over function is disabl ed, the pcf8523 works only with the power supply v dd . [2] when the battery switch-over function is disabl ed, the pcf8523 works only with the power supply v dd . v bat must be put to ground and the battery low detection function is disabled. [3] default value. 8.5.1 standby mode when the device is first powered up from the battery (v bat ) but without a main supply (v dd ), the pcf8523 automatically enters the standby mode. in standby mode, the pcf8523 does not draw any power from the back up battery until the device is powered up from the main power supply v dd . thereafter, the device switches over to battery backup mode whenever the main power supply v dd is lost. it is also possible to enter into standby mode when the chip is already supplied by the main power supply v dd and a backup battery is connect ed. to enter the standby mode, the power management control bits pm[2:0] have to be set logic 111. then the main power supply v dd must be removed. as a result of it, the pcf8523 enters the standby mode and does not draw any current from the backup battery before it is powered up again from main supply v dd . table 11. power management function control bits pm[2:0] function 000 battery switch-over function is enabled in standard mode; battery low detection function is enabled 001 battery switch-over function is enabled in direct switching mode; battery low detection function is enabled 010,011 [1] battery switch-over function is disabled - only one power supply (v dd ); battery low detection function is enabled 100 battery switch-over function is enabled in standard mode; battery low detection function is disabled 101 battery switch-over function is enabled in direct switching mode; battery low detection function is disabled 110 not allowed 111 [2] [3] battery switch-over function is disabled - only one power supply (v dd ); battery low detection function is disabled pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 16 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.5.2 battery switch-over function the pcf8523 has a backup battery switch-over ci rcuit. it monitors the main power supply v dd and switches automatically to the backup battery when a power failure condition is detected. one of two operation modes can be selected: ? standard mode: the power failure condition happens when: v dd < v bat and v dd pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 19 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar an unreliable battery does not ensure data integrity during periods of backup battery operation. when v bat drops below the threshold value v th(bat)low , the following sequence occurs (see figure 11 ): 1. the battery low flag blf is set logic 1 2. an interrupt is generated if the control bit blie (register control_3) is enabled. the interrupt remains active until the battery is replaced (blf set logic 0) or when bit blie is disabled (blie set logic 0) 3. the flag blf (register control_3) remains logic 1 until the battery is replaced. blf cannot be cleared using the interface. it is cleared automatically by the battery low detection circuit when the battery is replaced 8.6 time and date registers most of these registers are coded in the binary coded de cimal (bcd) format. bcd is used to simplify application use. an example is shown for the array seconds in ta b l e 1 3 . fig 11. battery low detection behavior with bit blie set logic 1 (enabled) 013aaa323 internal power supply (= v bbs ) v bat blf v th(bat)low (= 2.5 v) v bat v dd = v bbs int1 pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 20 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.6.1 register seconds [1] start-up value. 8.6.1.1 oscillator stop flag the os flag is set whenever the oscillator is stopped (see figure 12 ). the flag remains set until cleared by using the interface. when t he oscillator is not running, then the os flag cannot be cleared. this method can be used to monitor the oscillator. the oscillator may be st opped, for example, by grounding one of the oscillator pins, osci or osco. the oscillator is also considered to be stopped duri ng the time between power-on and stable crystal resonance. this time may be in a range of 200 ms to 2 s, depending on crystal type, temperature, and supply voltage. at power-on, the os flag is always set. table 12. seconds - seconds and clock integrity status register (address 03h) bit description bit symbol value place value description 7 os 0 - clock integrity is guaranteed 1 [1] - clock integrity is not guaranteed; oscillator has stopped or been interrupted 6 to 4 seconds 0 to 5 ten?s place actual seconds coded in bcd format 3 to 0 0 to 9 unit place table 13. seconds coded in bcd format seconds value in decimal upper-digit (ten?s place) digit (unit place) bit bit 6 5 4 3 2 1 0 00 0000000 01 0000001 02 0000010 : ::::::: 09 0001001 10 0010000 : ::::::: 58 1011000 59 1011001 pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 21 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.6.2 register minutes 8.6.3 register hours [1] hour mode is set by bit 12_24 in register control_1 (see table 7 ). 8.6.4 register days [1] if the year counter contains a value, which is exactl y divisible by 4 (includi ng the year 00), the pcf8523 compensates for leap years by adding a 29 th day to february. fig 12. os flag 013aaa319 os = 1 and flag can not be cleared os = 1 and flag can be cleared t v dd oscillation os flag os flag cleared by software os flag set when oscillation stops oscillation now stable table 14. minutes - minutes register (address 04h) bit description bit symbol value place value description 7 - - - unused 6 to 4 minutes 0 to 5 ten?s place actual minutes coded in bcd format 3 to 0 0 to 9 unit place table 15. hours - hours register (address 05h) bit description bit symbol value place value description 7 to 6 - - - unused 12 hour mode [1] 5 ampm 0 - indicates am 1 - indicates pm 4 hours 0 to 1 ten?s place actual hours in 12 hour mode coded in bcd format 3 to 0 0 to 9 unit place 24 hour mode [1] 5 to 4 hours 0 to 2 ten?s place actual hours in 24 hour mode coded in bcd format 3to0 0to9 unit place table 16. days - days register (address 06h) bit description bit symbol value place value description 7 to 6 - - - unused 5to4 days [1] 0 to 3 ten?s place actual day coded in bcd format 3to0 0to9 unit place pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 22 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.6.5 register weekdays [1] definition may be reassigned by the user. 8.6.6 register months table 17. weekdays - weekdays register (address 07h) bit description bit symbol value description 7 to 3 - - unused 2to0 weekdays 0to6 actual weekday, values see ta b l e 1 8 table 18. weekday assignments day [1] bit 2 1 0 sunday 0 0 0 monday 0 0 1 tuesday 0 1 0 wednesday 0 1 1 thursday 1 0 0 friday 1 0 1 saturday110 table 19. months - months register (address 08h) bit description bit symbol value place value description 7 to 5 - - - unused 4 months 0 to 1 ten?s place actual month coded in bcd format; assignments see table 20 3 to 0 0 to 9 unit place table 20. month assignments in bcd format month upper-digit (ten?s place) digit (unit place) bit bit 4 3 2 1 0 january 0 0 0 0 1 february 0 0 0 1 0 march 0 0 0 1 1 april00100 may00101 june00110 july00111 august01000 september 0 1 0 0 1 october10000 november10001 december10010 pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 23 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.6.7 register years 8.6.8 data flow of the time function figure 13 shows the data flow and data dependencies starting from the 1 hz clock tick. during read/write operations, the time counting circuits (memory locations 03h through 09h) are blocked. the blocking prevents: ? faulty reading of the clock and calendar during a carry condition ? incrementing the time regist ers during the read cycle after the read/wri te-access is completed, the time circuit is released again and any pending request to increment the time counte rs that occurred during the read/write access is serviced. a maximum of one request can be stored; therefore, all accesses must be completed within 1 second (see figure 14 ). table 21. years - years register (09h) bit description bit symbol value place value description 7 to 4 years 0 to 9 ten?s place actual year coded in bcd format 3to0 0to9 unit place fig 13. data flow diagram of the time function fig 14. access time for read/write operations 013aaa324 1 hz tick 12/24 hour mode weekdays seconds minutes hours days leap year calculation months years t < 1 s 013aaa215 slave address data stop data start pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 24 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar because of this method, it is very important to make a read or write access in one go, that is, setting or reading seconds through to years should be made in one single access. failing to comply with this method could result in th e time becoming corrupted. as an example, if the time (seconds through to hours) is set in one access and then in a second access the date is set, it is possible that the time will increment between the two accesses. a similar pr oblem exists when reading. a rollover may occur between reads thus giving the minutes from one moment and the hours from the next. 8.7 alarm registers the registers at addresses 0ah throu gh 0dh contain the alarm information. 8.7.1 register minute_alarm [1] default value. 8.7.2 register hour_alarm [1] default value. [2] hour mode is set by bit 12_24 in register control_1 (see table 7 ). table 22. minute_alarm - minute alarm register (address 0ah) bit description bit symbol value place value description 7 ae_m 0 - minute alarm is enabled 1 [1] - minute alarm is disabled 6 to 4 minute_alarm 0 to 5 ten?s place minute alarm information coded in bcd format 3 to 0 0 to 9 unit place table 23. hour_alarm - hour alarm regist er (address 0bh) bit description bit symbol value place value description 7 ae_h 0 - hour alarm is enabled 1 [1] - hour alarm is disabled 6 - - - unused 12 hour mode [2] 5 ampm 0 - indicates am 1 - indicates pm 4 hour_alarm 0 to 1 ten?s place hour alarm information in 12 hour mode coded in bcd format 3 to 0 0 to 9 unit place 24 hour mode [2] 5 to 4 hours 0 to 2 ten?s place hour alarm information in 24 hour mode coded in bcd format 3to0 0to9 unit place pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 25 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.7.3 register day_alarm [1] default value. 8.7.4 register weekday_alarm [1] default value. 8.7.5 alarm flag table 24. day_alarm - day alarm register (address 0ch) bit description bit symbol value place value description 7 ae_d 0 - day alarm is enabled 1 [1] - day alarm is disabled 6 - - - unused 5 to 4 day_alarm 0 to 3 ten?s place day alarm information coded in bcd format 3 to 0 0 to 9 unit place table 25. weekday_alarm - weekday alarm re gister (address 0dh) bit description bit symbol value description 7 ae_w 0 weekday alarm is enabled 1 [1] weekday alarm is disabled 6 to 3 - - unused 2 to 0 weekday_alarm 0 to 6 weekday alarm information (1) only when all enabled alarm settings are matching. it is only on increment to a matched case that the alarm flag is set, see section 8.7.5 . fig 15. alarm function block diagram 013aaa088 weekday alarm ae_w weekday time = day alarm ae_d day time = hour alarm ae_h hour time = minute alarm ae_m minute time = check now signal set alarm flag af (1) ae_m = 1 1 0 example pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 26 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar when one or several alarm registers are loaded with a valid minute, hour, day, or weekday value and its corresponding alarm enable bit (ae_x) is logic 0, then that information is compared with the current minute, hour, day, and weekday value. when all enabled comparisons first match, the alarm flag, af (register control_2), is set logic 1. the generation of interrupts from the alarm function is controlled via bit aie (register control_1). if bit aie is enabled, then the int1 pin follows the condition of bit af. af remains set until cleared by th e interface. once af has been cleared, it will only be set again when the time increments to match the al arm condition once more. alarm registers, which have their ae_x bit logic 1 are ignored. the generation of interrupts from the alarm function is described more detailed in section 8.4 . ta b l e 2 6 and ta b l e 2 7 show an example for clearing bit af. clearing the flag is made by a write command, therefore bits 2, 1, and 0 must be re-written with their previous values. repeatedly re-writing these bits has no influence on the functional behavior. to prevent the timer flags being overwritten wh ile clearing bit af, logic and is performed during a write access. a flag is cleared by wr iting logic 0 while a fl ag is not cleared by writing logic 1. writing logic 1 results in the flag value remaining unchanged. ta b l e 2 7 shows what instruction must be sent to clear bit af. in this example, bit ctaf, ctbf, and bit sf are unaffected. [1] the bits labeled as - have to be re written with the previous values. example where only the minute alarm is used and no other interrupts are enabled. fig 16. alarm flag timing table 26. flag location in register control_2 register bit 7 6 5 4 3 2 1 0 control_2 wtaf ctaf ctbf sf af - - - table 27. example to clear only af (bit 3) register bit [1] 7 6 5 4 3 2 1 0 control_201110- - - 001aaf903 44 45 45 minute alarm minutes counter af int when aie = 1 46 pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 27 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.7.6 alarm interrupts generation of interrupts from the alarm function is controlled via the bit aie (register control_1). if aie is enabled, the int1 follows the status of bit af (register control_2). clearing af immediately clears int1 . no pulse generation is possible for alarm interrupts. example where only the minute alarm is used and no other interrupts are enabled. fig 17. af timing 013aaa335 44 45 minute counter minute alarm af int1 scl instruction 45 clear instruction pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 28 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.8 register offset the pcf8523 incorporates an offset register (address 0eh), which can be used to implement several functions, like: ? aging adjustment ? temperature compensation ? accuracy tuning [1] default value. for mode = 0, each lsb introduces an offs et of 4.34 ppm. for mode = 1, each lsb introduces an offset of 4.069 ppm. the valu es of 4.34 ppm and 4.069 ppm are based on a nominal 32.768 khz clock. the offset value is coded in two?s complement giving a range of +63 lsb to ? 64 lsb. [1] default mode. the correction is made by adding or subtra cting clock correction pulses, thereby changing the period of a single second. it is possible to monitor when correction pulses are applied. to enable correction interrupt generation, bit cie (register control_1) has to be set logic 1. at every correction cycle a 1 4096 s pulse is generated on pin intx . if multiple correction pulses are applied, a 1 4096 s interrupt pulse is generated for each correction pulse applied. table 28. offset - offset register (address 0eh) bit description bit symbol value description 7mode 0 [1] offset is made once every two hours 1 offset is made once every minute 6 to 0 offset[6:0] see ta b l e 2 9 offset value table 29. offset values offset[6:0] offset value in decimal offset value in ppm every two hours (mode = 0) every minute (mode = 1) 0111111 +63 +273.420 +256.347 0111110 +62 +269.080 +252.278 :::: 0000010 +2 +8.680 +8.138 0000001 +1 +4.340 +4.069 0000000 0 [1] 0 [1] 0 [1] 1111111 ? 1 ? 4.340 ? 4.069 1111110 ? 2 ? 8.680 ? 8.138 :::: 1000001 ? 63 ? 273.420 ? 256.347 1000000 ? 64 ? 277.760 ? 260.416 pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 29 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.8.1 correction when mode = 0 the correction is triggered once per two hours and then correction pulses are applied once per minute until the programmed correction values have been implemented. [1] the correction pulses on pin int1 are 1 64 s wide. in mode = 0, any timer or clock output using a frequency below 64 hz is affected by the clock correction (see ta b l e 3 1 ). table 30. correction pulses for mode = 0 correction value hour minute correction pulses on int1 per minute [1] +1 or ? 102001 +2 or ? 2 02 00 and 01 1 +3 or ? 3 02 00, 01, and 02 1 :::: +59 or ? 59 02 00 to 58 1 +60 or ? 60 02 00 to 59 1 +61 or ? 61 02 00 to 59 1 03 00 1 +62 or ? 62 02 00 to 59 1 03 00 and 01 1 +63 or ? 63 02 00 to 59 1 03 00, 01, and 02 1 ? 64 02 00 to 59 1 03 00, 01, 02, and 03 1 table 31. effect of clock correction for mode = 0 clkout frequency (hz) effect of correction timer source clock frequency (hz) effect of correction 32768 no effect 4096 no effect 16384 no effect 64 no effect 8192 no effect 1 affected 4096 no effect 1 60 affected 1024 no effect 1 3600 affected 32 affected - - 1affected-- pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 30 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.8.2 correction when mode = 1 the correction is triggered once per minute and then correction pulses are applied once per second up to a maximum of 60 pulses. when correction values greater than 60 pulses are used, additional correction pulses are made in the 59 th second. clock correction is made more frequently in mode = 1; however, this can result in higher power consumption. [1] the correction pulses on pin intx are 1 4096 s wide. for multiple pulses, they are repeated at an interval of 1 2048 s. in mode = 1, any timer source clock using a frequency below 4.096 khz is also affected by the clock correction (see ta b l e 3 3 ). table 32. correction pulses for mode = 1 correction value minute second correction pulses on int1 per second [1] +1 or ? 102001 +2 or ? 2 02 00 and 01 1 +3 or ? 3 02 00, 01, and 02 1 :::: +59 or ? 59 02 00 to 58 1 +60 or ? 60 02 00 to 59 1 +61 or ? 61 02 00 to 58 1 02 59 2 +62 or ? 62 02 00 to 58 1 02 59 2 +63 or ? 63 02 00 to 58 1 02 59 4 ? 64 02 00 to 58 1 02 59 5 table 33. effect of clock correction for mode = 1 clkout frequency (hz) effect of correction timer source clock frequency (hz) effect of correction 32768 no effect 4096 no effect 16384 no effect 64 affected 8192 no effect 1 affected 4096 no effect 1 60 affected 1024 no effect 1 3600 affected 32 affected - - 1affected-- pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 31 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.8.3 offset calibration workflow the calibration offset has to be calculated based on the time. figure 18 shows the workflow how the offset register values can be calculated: fig 18. offset calibratio n calculation workflow measure the frequency on pin clkout: f meas convert to time: t meas = 1 / f meas calculate the difference to the ideal period of 1 / 32768.00: d meas = 1 / 32768 - t meas calculate the ppm deviation compared to the measured value: e ppm = 1000000 d meas / t meas calculate the offset register value: mode = 0 (low power): offset value = e ppm / 4.34 mode = 1 (fast correction) offset value = e ppm / 4.069 013aaa683 example 32768.48 hz 30.5171 s 0.000447 s 14.6484 ppm 3.375 3 correction pulses are needed 3.600 4 correction pulses are needed pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 32 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.9 timer function the pcf8523 has three timers: ? timer a can be used as a watchdog timer or a countdown timer (see section 8.9.2 ). it can be configured by using tac[1:0] in the tmr_clkout_c trl register (0fh) ? timer b can be used as a countdown timer (see section 8.9.3 ). it can be configured by using tbc in the tmr_cl kout_ctrl register (0fh) ? second interrupt timer is used to generate an interrupt once per second (see section 8.9.4 ) timer a and timer b both have five sele ctable source clocks allowing for countdown periods from less than 1 ms to 255 h. to cont rol the timer functions and timer output, the registers 01h, 0fh, 10h, 11h, 12h, and 13h are used. 8.9.1 timer registers 8.9.1.1 register tmr_clkout_ctrl and clock output [1] default value. 8.9.1.2 clkout frequency selection clock output operation is controlled by the cof[2:0] in the tmr_clkout_ctrl register. frequencies of 32.768 khz (default) down to 1 hz can be generated (see ta b l e 3 5 ) for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. table 34. tmr_clkout_ctrl - timer and clkout control register (address 0fh) bit description bit symbol value description 7tam 0 [1] permanent active interrupt for timer a and for the second interrupt timer 1 pulsed interrupt for timer a and the second interrupt timer 6tbm 0 [1] permanent active interrupt for timer b 1 pulsed interrupt for timer b 5 to 3 cof[2:0] see ta b l e 3 5 clkout frequency selection 2 to 1 tac[1:0] 00 [1] to 11 timer a is disabled 01 timer a is configured as countdown timer if ctaie (register control_2) is set logic 1, the interrupt is activated when the countdown timed out 10 timer a is configured as watchdog timer if wtaie (register control_2) is set logic 1, the interrupt is activated when timed out 0tbc 0 [1] timer b is disabled 1 timer b is enabled if ctbie (register control_2) is set logic 1, the interrupt is activated when the countdown timed out pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 33 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar a programmable square wave is available at pin int1 /clkout and pin clkout, which are both open-drain outputs. pin int1 /clkout has both functions of int1 and clkout combined. the duty cycle of the selected clock is not c ontrolled but due to the nature of the clock generation, all clock frequencies except 32.768 khz have a duty cycle of 50 : 50. the stop bit function can also affect the clkout signal, depending on the selected frequency. when stop is active, the int1 /clkout and clkout pins are high-impedance for all frequencies except of 32.768 khz, 16.384 khz and 8.192 khz. for more details, see section 8.10 . [1] duty cycle definition: % high-level time : % low-level time. [2] default value. [3] clock frequencies may be affected by offset correction. 8.9.1.3 register tmr_a_freq_ctrl [1] default value. table 35. clkout frequency selection cof[2:0] clkout frequency (hz) typical duty cycle [1] effect of stop bit 000 [2] 32768 60 : 40 to 40 : 60 no effect 001 16384 50 : 50 no effect 010 8192 50 : 50 no effect 011 4096 50 : 50 clkout = high-z 100 1024 50 : 50 clkout = high-z 101 32 50 : 50 [3] clkout = high-z 110 1 50 : 50 [3] clkout = high-z 111 clkout disabled (high-z) table 36. tmr_a_freq_ctrl - timer a frequency control register (address 10h) bit description bit symbol value description 7 to 3 - - unused 2 to 0 taq[2:0] source clock for timer a (see table 40 ) 000 4.096 khz 001 64 hz 010 1 hz 011 1 60 hz 111 [1] 110 100 1 3600 hz pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 34 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.9.1.4 register tmr_a_reg 8.9.1.5 register tmr_b_freq_ctrl [1] default value. 8.9.1.6 register tmr_b_reg table 37. tmr_a_reg - timer a value regi ster (address 11h) bit description bit symbol value description 7 to 0 timer_a_value[7:0] 00 to ff timer-period in seconds where n is the countdown value timerperiod n sourceclockfrequency ---------------------------------------------------------- - = table 38. tmr_b_freq_ctrl - timer b frequency control register (address 12h) bit description bit symbol value description 7 - - unused 6 to 4 tbw[2:0] low pulse width for pulsed timer b interrupt 000 [1] 46.875 ms 001 62.500 ms 010 78.125 ms 011 93.750 ms 100 125.000 ms 101 156.250 ms 110 187.500 ms 111 218.750 ms 3 - - unused 2 to 0 tbq[2:0] source clock for timer b (see table 40 ) 000 4.096 khz 001 64 hz 010 1 hz 011 1 60 hz 111 [1] 110 100 1 3600 hz table 39. tmr_b_reg - timer b value register (address 13h) bit description bit symbol value description 7 to 0 timer_b_value[7:0] 00 to ff timer-period in seconds where n is the countdown value timerperiod n sourceclockfrequency ---------------------------------------------------------- - = pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 35 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.9.1.7 programmable ti mer characteristics 8.9.2 timer a with the bit field tac[1:0] in register tmr_ clkout_ctrl (0fh) timer a can be configured as a countdown timer (tac[1:0] = 01) or watchdog timer (tac[1:0] = 10). 8.9.2.1 watchdog timer function the 3 bits taq[2:0] in register tmr_a_freq_ctrl (10h) determine one of the five source clock frequencies for the watchdog timer: 4.096 khz, 64 hz, 1 hz, 1 60 hz or 1 3600 hz (see ta b l e 3 6 ). the generation of interrupts from the watchd og timer is controlled by using wtaie bit (register control_2). when configured as a watchdog timer (tac[1 :0] = 10), the 8-bit timer value in register tmr_a_reg (11h) determines the watchdog timer-period. the watchdog timer counts down from value n in register tmr_a_reg (11h). when the counter reaches 1, the watchdog timer flag wtaf (register control_2) is set logic 1 on the next rising edge of the timer clock (see figure 19 ). in that case: ? if wtaie = 1, an inte rrupt will be generated ? if wtaie = 0, no inte rrupt will be generated the interrupt generated by the watchdog timer function of timer a may be generated as pulsed signal or a permanentiy active signal . the tam bit (register tmr_clkout_ctrl) is used to control the interrupt generation mode. the counter does not automatically reload. when loading the counter with any valid value of n, except 0: ? the flag wtaf is reset (wtaf = 0) ? interrupt is cleared ? the watchdog timer starts table 40. programmable timer characteristics taq[2:0] tbq[2:0] timer source clock frequency units minimum timer-period (n = 1) units maximum timer-period (n = 255) units 000 4.096 khz 244 ? s 62.256 ms 001 64 hz 15.625 ms 3.984 s 010 1 hz 1 s 255 s 011 1 60 hz 1 min 255 min 111 110 100 1 3600 hz 1 hour 255 hour pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 36 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar when loading the counter with 0: ? the flag wtaf is reset (wtaf = 0) ? interrupt is cleared ? the watchdog timer stops wtaf is read only. a read of the register control_2 (01h) automatically resets wtaf (wtaf = 0) and clears the interrupt. 8.9.2.2 countdown timer function when configured as a countdown timer (tac[1:0] = 01), timer a counts down from the software programmed 8-bit binary value n in register tmr_a_reg (11h). when the counter reaches 1, the following events occur on the next rising edge of the timer clock (see figure 20 ): ? the countdown timer flag ctaf (register control_2) is set logic 1 ? when the interrupt generation is enabled (ctaie = 1), an interrupt signal on int1 is generated ? the counter automatically reloads ? the next timer-period starts tac[1:0] = 10, wtaie = 1, wtaf = 1, an interrupt is generated. fig 19. watchdog activates an interrupt when timed out 013aaa327 watchdog timer value wtaf n = 0 n mcu int1 n = 1 pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 37 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar at the end of every countdown, the timer sets the countdown timer flag ctaf (register control_2). ctaf may only be cleared by using the interface. instructions, how to clear a flag, is given in section 8.7.5 . when reading the timer, the current countdown value is returned and not the initial value n. since it is not possible to freeze the countdown timer counter during read back, it is recommended to read the register twice and check for consistent results. if a new value of n is written before the end of the actual timer-period, this value takes immediate effect. it is not recommended to change n without first disabling the counter by setting tac[1:0] = 00 (register tmr_clkout_ctr l). the update of n is asynchronous to the timer clock. therefore changing it on the fly could result in a corrupted value loaded into the countdown counter. this can result in an undetermined countdown period for the first period. the countdown value n will be correctly stored and correctly loaded on subsequent timer-periods. loading the counter with 0 effectively stops the timer. when starting the countdown timer for the firs t time, only the first period does not have a fixed duration. the amount of inaccuracy for t he first timer-period depends on the chosen source clock, see table 41 . the generation of interrupts from the countdown timer is controlled via the ctaie bit (register control_2). in this example, it is assumed that the count down timer flag (ctaf) is cleared before the next countdown period expires and that the interrupt output is set to pulse mode. fig 20. general countdown timer behavior table 41. first period delay for timer counter value n timer source clock minimum timer-period maximum timer-period 4.096 khz n n + 1 64 hz n n + 1 1 hz (n ? 1) + 1 64 hz n + 1 64 hz 1 60 hz (n ? 1) + 1 64 hz n + 1 64 hz 1 3600 hz (n ? 1) + 1 64 hz n + 1 64 hz 013aaa328 countdown value, n timer source clock countdown counter wd/cd [1:0] ctaf int1 02 03 00 01 xx 03xx 01 03 02 01 03 02 n duration of first timer period after enable may range from n?1 to n+1 n 01 03 pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 38 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar when the interrupt generation is enabled (ctaie = 1) and the countdown timer flag ctaf is set logic 1, an interrupt signal on int1 is generated. the interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal, which follows the condition of ctaf (register control_2). the tam bit (register tmr_clkout_ctrl) is used to control this mode sele ction. the interrupt output may be disabled with the ctaie bit (register control_2). 8.9.3 timer b timer b can only be used as a countdown ti mer and can be switched on and off by the tbc bit in register tmr_clkout_ctrl (0fh). the generation of interrupts from the countdown timer is controlled via the ctbie bit (register control_2). when enabled, it counts down from the software programmed 8 bit binary value n in register tmr_b_reg (13h). when the counte r reaches 1 on the next rising edge of the timer clock, the following events occur (see figure 21 ): ? the countdown timer flag ctbf (register control_2) is set logic 1 ? when the interrupt generation is enabled (ctbie = 1), interrupt signals on int1 and int2 are generated ? the counter automatically reloads ? the next timer-period starts at the end of every countdown, the timer sets the countdown timer flag ctbf (register control_2). ctbf may only be cleared by using the interface. instructions, how to clear a flag, is given in section 8.7.5 . when reading the timer, the current countdown value is returned and not the initial value n. since it is not possible to freeze the countdown timer counter during read back, it is recommended to read the register twice and check for consistent results. in this example, it is assumed that the count down timer flag (ctbf) is cleared before the next countdown period expires and that inte rrupt output is set to pulse mode. fig 21. general countdown timer behavior 013aaa329 countdown value, n timer source clock countdown counter wd/cd [1:0] ctbf int1/int2 02 03 00 01 xx 03xx 01 03 02 01 03 02 n duration of first timer period after enable may range from n?1 to n+1 n 01 03 pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 39 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar if a new value of n is written before the end of the actual timer-period, this value will take immediate effect. it is not recommended to change n without first disabling the counter by setting tbc logic 0 (register tmr_clkout_ctrl). the update of n is asynchronous to the timer clock. therefore changing it on the fly could result in a corrupted value loaded into the countdown counter. this can result in an undetermined countdown period for the first period. the countdown valu e n will be correctly stored and correctly loaded on subsequent timer-periods. loading the counter with 0 effectively stops the timer. when starting the countdown timer for the firs t time, only the first period does not have a fixed duration. the amount of inaccuracy for t he first timer-period depends on the chosen source clock; see table 41 . when the interrupt generation is enabled (ctbie = 1) and the countdown timer flag ctaf is set logic 1, interrupt signals on int1 and int2 are generated. the interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal, which follows the condition of ctbf (reg ister control_2). the tbm bit (register tmr_clkout_ctrl) is used to control this mode selection. interrupt output may be disabled with the ctbie bi t (register control_2). 8.9.4 second interrupt timer pcf8523 has a pre-defined timer, which is us ed to generate an interrupt once per second. the pulse generator for the second interrupt timer operates from an internal 64 hz clock and generates a pulse of 1 64 s in duration. it is independent of the watchdog or countdown timer and can be switched on and off by the sie bit in register control_1 (00h). the interrupt generated by the second interrupt timer may be generated as pulsed signal every second or as a permanently active signal. the tam bit (register tmr_clkout_ctrl) is used to control the interrupt generation mode. when the second interrupt timer is enabled (sie = 1), then the timer sets the flag sf (register control_2) every second (see ta b l e 4 2 ). sf may only be cleared by using the interface. instructions, how to clear a flag, are given in section 8.7.5 . when sf is logic 1: ? if tam (register tmr_clkout_ctrl) is logic 1, the interrupt is generated as a pulsed signal every second ? if tam is logic 0, the interrupt is a permanent ly active signal that remains, until sf is cleared table 42. effect of bit sie on int1 and bit sf sie result on int1 result on sf 0 no interrupt generated sf never set 1 an interrupt once per second sf set when seconds counter increments pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 40 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.9.5 timer interrupt pulse the timer interrupt is generated as a pulsed signal when tam or tbm are set logic 1. the pulse generator for the timer interrupt also uses an internal clock, but this time it is dependent on the selected source clock for the timer and on the timer register value n. so, the width of the interrupt pulse varies; see table 43 and ta b l e 4 4 . [1] n = loaded timer register value. timer stops when n = 0. for timer b, interrupt pulse width is programmable via bit tbm (register tmr_clkout_ctrl). in this example, bit tam is set logic 1 and t he sf flag is not cleared after an interrupt. fig 22. example for second interrupt when tam = 1 in this example, bit tam is set logic 0 and the sf flag is cleared after an interrupt. fig 23. example for second interrupt when tam = 0 013aaa331 58 59 59 00 11 seconds counter minutes counter int1 when sie enabled sf when sie enabled 12 00 01 013aaa332 58 seconds counter minutes counter int1 when sie enabled sf when sie enabled 59 59 11 00 00 01 12 table 43. interrupt low pu lse width for timer a pulse mode, bit tam set logic 1. source clock (hz) interrupt pulse width n = 1 [1] n > 1 [1] 4096 122 ? s 244 ? s 64 7.812 ms 15.625 ms 1 15.625 ms 15.625 ms 1 60 15.625 ms 15.625 ms 1 3600 15.625 ms 15.625 ms pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 41 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar [1] n = loaded timer register value. timer stops when n = 0. [2] if pulse period is shorter than the setting via bit tbw[2:0], the interrupt pulse width is set to 15.625 ms. when flags like sf, ctaf, wtaf, and ctbf are cleared before the end of the interrupt pulse, then the interrupt pulse is shortened. th is allows the source of a system interrupt to be cleared immediately when it is serviced, th at is, the system does not have to wait for the completion of the pulse before continuing; see figure 24 and figure 25 . instructions for clearing flags can be found in section 8.7.5 . instructions for clearing the bit wtaf can be found in section 8.9.2.1 . table 44. interrupt low pu lse width for timer b pulse mode, bit tbm set logic 1. source clock (hz). interrupt pulse width n = 1 [1] n > 1 [1] 4096 122 ? s 244 ? s 64 7.812 ms see ta b l e 3 8 [2] 1 see table 38 : 1 60 :: 1 3600 :: (1) indicates normal duration of int1 pulse. the timing shown for clearing bit sf is also vali d for the non-pulsed interrupt mode, that is, when tam set logic 0, where the int1 pulse may be shortened by setting sie logic 0. fig 24. example of shortening the int1 pulse by clearing the sf flag 013aaa333 58 seconds counter sf int1 scl instruction 59 clear instruction (1) pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 42 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar (1) indicates normal duration of int1 pulse. the timing shown for clearing ctaf is also valid for the non-pulsed interrupt mode, that is, when tam set logic 0, where the int1 pulse may be shortened by setting ctaie logic 0. fig 25. example of shortening the int1 pulse by clearing the ctaf flag 013aaa334 01 countdown counter cdtf int1 scl instruction n clear instruction (1) pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 43 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.10 stop bit function the stop bit function allows the accurate st arting of the time circuits. the stop bit function causes the upper part of the prescaler (f 2 to f 14 ) to be held in reset and thus no 1 hz ticks are generated. the time circuits can then be set and do not increment until the stop bit is released (see figure 26 ). stop does not affect the output of 32. 768 khz, 16.384 khz or 8.192 khz (see section 8.9.1.1 ). the lower two stages of the prescaler (f 0 and f 1 ) are not reset. and because the i 2 c-bus interface is asynchronous to t he crystal oscillator, the accu racy of re-starting the time circuits will be between 0 an d one 8.192 khz cycle (see figure 27 ). the first increment of the time circuits is between 0.499878 s and 0.500000 s after stop is released. the uncertainty is caused by the prescaler bits f 0 and f 1 not being reset (see ta b l e 4 5 ). fig 26. stop bit fig 27. stop bit release timing 013aaa336 osc 32768 hz 16384 hz osc stop detector f 0 f 1 f 13 res f 14 res f 2 res 2 hz 512 hz 16384 hz 8192 hz 1 hz tick stop clkout source oscillator stop flag 8192 hz 4096 hz 001aaf912 8192 hz stop released 0 s to 122 s pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 44 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar [1] f 0 is clocked at 32.768 khz. table 45. first increment of time circuits after stop release bit prescaler bits [1] 1hz tick time comment stop f 0 f 1 -f 2 to f 14 hh:mm:ss clock is running normally 0 01-0000111010100 12:45:12 prescaler counting normally stop is activated by user; f 0 f 1 are not reset and values cannot be predicted externally 1 xx-0000000000000 12:45:12 prescaler is reset; time circuits are frozen new time is set by user 1 xx-0000000000000 08:00:00 prescaler is reset; time circuits are frozen stop is released by user 0 xx-0000000000000 08:00:00 prescaler is now running 0 xx-1000000000000 08:00:00 - 0 xx-0100000000000 08:00:00 - 0 xx-1100000000000 08:00:00 - :: : : 0 11-1111111111110 08:00:00 - 0 00-0000000000001 08:00:01 0 to 1 transition of f14 increments the time circuits 0 10-0000000000001 08:00:01 - :: : : 0 11-1111111111111 08:00:01 - 0 00-0000000000000 08:00:01 - :: : : 0 11-1111111111110 08:00:01 - 0 00-0000000000001 08:00:02 0 to 1 transition of f14 increments the time circuits 013aaa337 0.499878 s to 0.500000 s 1 s pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 45 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 8.11 i 2 c-bus interface the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines are connected to a positive supply via a pull-up re sistor. data transfer is initiated only when the bus is not busy. 8.11.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line remains stable during the high period of the clock pulse as changes in the data line at this time are interpreted as control signals (see figure 28 ). 8.11.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high, is defined as the start condition (s). a low-to-high transition of the data line, while the clock is high, is defined as the stop condition (p) (see figure 29 ). for this device, a repeated start is not allowed. therefore, a stop has to be released before the next start. 8.11.3 system configuration a device generating a message is a transmit ter; a device receiving a message is the receiver. the device that controls the message is the master and the devices, which are controlled by the master, are the slaves. fig 28. bit transfer mbc621 data line stable; data valid change of data allowed sda scl fig 29. definition of start and stop conditions mbc622 sda scl p stop condition sda scl s start condition pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 46 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar the pcf8523 can act as a slave transmitter and a slave receiver. 8.11.4 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is un limited. each byte of 8 bits is followed by an acknowledge cycle. ? a slave receiver, which is addressed, must generate an acknowledge cycle after the reception of each byte ? also a master receiver must generate an acknowledge cycle after the reception of each byte that has been clocke d out of the slave transmitter ? the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the related acknowledge clock pulse (set-up and hold times must be considered) ? a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge cycle on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition acknowledgement on the i 2 c-bus is shown in figure 31 . 8.11.5 i 2 c-bus protocol one i 2 c-bus slave address (1101000) is reserved for the pcf8523. the entire i 2 c-bus slave address byte is shown in table 46 . fig 30. system configuration mba605 master transmitter receiver slave receiver slave transmitter receiver master transmitter master transmitter receiver sda scl fig 31. acknowledgement on the i 2 c-bus mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 47 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar [1] devices with other i 2 c-bus slave addresses can be produced on request. after a start condition, the i 2 c slave address has to be sent to the pcf8523 device. the r/w bit defines the direction of the following si ngle or multiple byte data transfer. for the format and the timing of the start condition (s), the stop condition (p) and the acknowledge bit (a) refer to the i 2 c-bus characteristics (see ref. 12 on page 67 ). in the write mode, a data transfer is terminated by sending either the stop condition or the start condition of the next data transfer. table 46. i 2 c slave address byte slave address [1] bit 7 6 5 4 3 2 1 0 msb lsb 1101000r/w fig 32. bus protocol for write mode 013aaa338 s 1 1 0 slave address register address 00h to 13h 0 to n data bytes write bit start/ stop acknowledge from pcf8523 acknowledge from pcf8523 acknowledge from pcf8523 1 0 0 0 0 a a a p/s fig 33. bus protocol for read mode 013aaa339 s 1 1 0 slave address 0 to n data bytes data byte last data byte read bit acknowledge from pcf8523 acknowledge from master no acknowledge 1 0 0 0 1 a a s 1 1 0 slave address register address 00h to 13h set register address read register data write bit stop acknowledge from pcf8523 acknowledge from pcf8523 1 0 0 0 0 a a p a p pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 48 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 9. internal circuitry fig 34. device diode protection diagram of pcf8523 013aaa340 clkout sda scl int1/clkout v dd osci osco v bat int2 v ss pcf8523 pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 49 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 10. limiting values [1] pass level; human body model (hbm), according to ref. 7 ? jesd22-a114 ? . [2] pass level; charged-device model (cdm), according to ref. 8 ? jesd22-c101 ? . [3] pass level; latch-up testing according to ref. 9 ? jesd78 ? at maximum ambient temperature (t amb(max) ). [4] according to the store and transport requirements (see ref. 13 ? um10569 ? ) the devices have to be stored at a temperature of +8 ? c to +45 ? c and a humidity of 25 % to 75 %. table 47. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +6.5 v i dd supply current ? 50 +50 ma v i input voltage ? 0.5 +6.5 v v o output voltage ? 0.5 +6.5 v i i input current ? 10 +10 ma i o output current ? 10 +10 ma v bat battery supply voltage ? 0.5 +6.5 v p tot total power dissipation - 300 mw v esd electrostatic discharge voltage hbm for all pcf8523 [1] - ? 2000 v cdm for all packaged pcf8523 [2] - ? 1500 v i lu latch-up current [3] -100ma t stg storage temperature [4] ? 65 +150 ?c t amb ambient temperature operating device ? 40 +85 ?c pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 50 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 11. static characteristics table 48. static characteristics v dd = 1.2 v to 5.5 v; v ss =0v; t amb = ? 40 ? c to +85 ? c; f osc = 32.768 khz; quartz r s =40k ? ; c l = 7 pf; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd supply voltage i 2 c-bus inactive; for clock data integrity t amb = ? 40 ? c to +85 ?c [1] 1.2- 5.5v t amb =+10 ? c to +85 ?c [2] 1.0- 5.5v i 2 c-bus active 1.6 - 5.5 v power management function active 1.8 - 5.5 v sr slew rate of v dd -- ? 0.5 v/ms v bat battery supply voltage power management function active 1.8 - 5.5 v i dd supply current i 2 c-bus active; f scl = 1000 khz - - 200 ? a i 2 c-bus inactive (f scl =0hz); interrupts disabled clock-out disabled; power management function disabled (pm[2:0] = 111) t amb =25 ?c; v dd =3.0v [3] -150-na t amb = ? 40 ? c to +85 ?c; v dd = 2.0 v to 5.0 v [3] - - 500 na clock-out enabled at 32 khz; power management function enabled (pm[2:0] = 000) t amb =25 ?c; v bat or v dd =3.0v [4] -1200-na t amb = ? 40 ? c to +85 ?c; v bat or v dd = 2.0 v to 5.0 v [4] - - 3600 na i l(bat) battery leakage current v dd active; v bat = 3.0 v - 50 100 na power management v th(sw)bat battery switch threshold voltage 2.28 2.5 2.7 v inputs [5] v il low-level input voltage - - 0.3v dd v v ih high-level input voltage 0.7v dd --v v i input voltage ? 0.5 - v dd +0.5 v i li input leakage current v i = v ss or v dd -0-na post esd event ? 1- +1 ? a c i input capacitance [6] --7pf pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 51 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar [1] for reliable oscillator start at power-up: v dd =v dd(min) +0.3v. [2] for reliable oscillator start at power-up: v dd =v dd(min) +0.5v. [3] timer source clock = 1 3600 hz, level of pins scl and sda is v dd or v ss . [4] when the device is supplied via the v bat pin instead of the v dd pin, the current values for i bat will be as specified for i dd under the same conditions. [5] the i 2 c-bus is 5 v tolerant. [6] implicit by design. [7] tested on sample basis. [8] integrated load capacitance, c l(itg) , is a calculation of c osci and c osco in series: . [9] tested at 25 ? c. [10] crystal characteri stic specification. outputs v o output voltage on pins int1 /clkout, clkout, int2, sda (refers to external pull-up voltage) ? 0.5 - 5.5 v v ol low-level output voltage v ss -0.4v i ol low-level output current output sink current; on pins int1 /clkout, clkout, int2 ; v ol =0.4v; v dd =5v [7] 1.5 - - ma on pin sda v ol =0.4v; v dd =3.0v [7] 20 - - ma i lo output leakage current v o =v ss or v dd -0-na post esd event ? 1- +1 ? a c l(itg) integrated load capacitance on pins osco, osci [8] [9] c l = 7 pf 3.3 7 14 pf c l = 12.5 pf 6 12.5 25 pf r s series resistance [10] - - 100 k ? table 48. static characteristics ?continued v dd = 1.2 v to 5.5 v; v ss =0v; t amb = ? 40 ? c to +85 ? c; f osc = 32.768 khz; quartz r s =40k ? ; c l = 7 pf; unless otherwise specified. symbol parameter conditions min typ max unit c litg ?? ? ?? ?? ------------------------------------------- - = pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 52 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 12. dynamic characteristics [1] fast mode plus guaranteed at 3.0 v < v dd <5.5v. [2] the minimum scl clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either the sda or scl is held low for a minimum of 25 ms. the bus ti me-out feature must be disabled for dc operation. [3] a master device must internally provide a hold time of at least 300 ns for the sda signal (refer to the v il of the scl signal) in order to bridge the undefined region of the falling edge of scl. [4] the maximum t f for the sda and scl bus lines is 300 ns. the maximum fall time for the sda output stage, t f is 250 ns. this allows series protection resistors to be connected between the sda pin, the scl pin and the sda/scl bus lines without exceeding the maximum t f . [5] t vd;ack = time for acknowledgement signal from scl low to sda output low. [6] t vd;dat = minimum time for valid sda output following scl low. [7] input filters on the sda and scl inputs suppr ess noise spikes of less than 50 ns. table 49. i 2 c-bus interface timing all timing characteristics are valid within the operating suppl y voltage and ambient temperature range and reference to 30 % and 70 % with an input voltage swing of v ss to v dd (see figure 35 ). symbol parameter conditions standard mode fast mode (fm) fast mode plus (fm+) [1] unit min max min max min max pin scl f scl scl clock frequency [2] - 100 - 400 - 1000 khz t low low period of the sc l clock - 4.7 - 1.3 - 0.5 - ? s t high high period of the sc l clock - 4.0 - 0.6 - 0.26 - ? s pin sda t su;dat data set-up time - 250 - 100 - 50 - ns t hd;dat data hold time - 0 - 0 - 0 - ns pins scl and sda t buf bus free time between a stop and start condition - 4.7 - 1.3 - 0.5 - ? s t su;sto set-up time for stop condition - 4.0 - 0.6 - 0.26 - ? s t hd;sta hold time (repeated) start condition - 4.0 - 0.6 - 0.26 - ? s t su;sta set-up time for a repeated start condition - 4.7 - 0.6 - 0.26 - ? s t r rise time of both sda and scl signals [3] [4] - 1000 20 + 0.1c b 300 - 120 ns t f fall time of both sda and scl signals [3] [4] - 300 20 + 0.1c b 300 - 120 ns c b capacitive load for each bus line - 400 - 400 - 550 pf t vd;ack data valid acknowledge time [5] - 3.45 - 0.9 - 0.45 ? s t vd;dat data valid time [6] - 3.45 - 0.9 - 0.45 ? s t sp pulse width of spikes that must be suppressed by the input filter [7] -50- 50- 50 ns pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 53 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 13. application information fig 35. i 2 c-bus timing diagram; rise and fall times refer to 30 % and 70 % scl sda t hd;sta t su;dat t hd;dat t f t buf t su;sta t low t high t vd;ack 013aaa417 t su;sto protocol start condition (s) bit 7 msb (a7) bit 6 (a6) bit 0 (r/w) acknowledge (a) stop condition (p) 1 /f scl t r t vd;dat r 1 and c 1 are recommended to limit the slew rate (sr, see table 48 ) of v dd . if v dd drops too fast, the internal supply switch to the battery is not guaranteed. fig 36. application diagram 013aaa341 pcf8523 osci osco int1/ clkout scl sda v dd v ss master transmitter receiver scl sda v dd v ss v bat clkout int2 v dd rr r: pull-up resistor r = c b r 1 c 1 t r pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 54 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 14. package outline fig 37. package outline sot96-1 (so8) of pcf8523t unit a max. a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 0.25 dimensions (inch dimensions are derived from the original mm dimensions) notes 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. 1.0 0.4 sot96-1 x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 4 5 pin 1 index 1 8 y 076e03 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.20 0.19 0.16 0.15 0.05 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.01 0.041 0.004 0.039 0.016 0 2.5 5 mm scale so8: plastic small outline package; 8 leads; body width 3.9 mm sot96-1 99-12-27 03-02-18 pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 55 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar fig 38. package outline sot909-1 (hvson8) of pcf8523tk 0.8 0.2 1 0.05 0.00 a 1 e h b unit d (1) y e 2.4 e 1 references outline version european projection issue date iec jedec jeita mm 4.1 3.9 cd h 2.35 2.05 y 1 4.1 3.9 3.25 2.95 0.4 0.3 0.05 0.1 dimensions (mm are the original dimensions) sot909-1 mo-229 e (1) 0.65 0.40 l 0.1 v 0.05 w 0 2 mm 1 scale sot909-1 hvson8: plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 4 x 4 x 0.85 mm a (1) max. 05-09-26 05-09-28 note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. x b terminal 1 index area e 1 e ac b v m c w m e h d h l 14 5 8 detail x a a 1 c c y c y 1 exposed tie bar (4) terminal 1 index area b a d e pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 56 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar fig 39. package outline sot402-1 (tssop14) of pcf8523ts unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot402-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 17 14 8 a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 a max. 1.1 pin 1 index pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 57 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 15. bare die outline [1] dimension includes saw lane. [2] p 1 and p 3 : pad size. [3] p 2 and p 4 : bump size. fig 40. bare die outline of pcf8523u pcf8523u_do european projection bare die; 12 bumps (6-6) pcf8523u detail y p 2 p 1 p 4 p 3 detail x a a 2 a 1 pc8523-1 x y 0 0 2 3 4 5 6 7 8 9 10 11 12 1 d e y x table 50. dimensions of pcf8523u original dimensions are in mm. unit (mm) a a 1 a 2 d [1] e [1] p 1 [2] p 2 [3] p 3 [2] p 4 [3] bump pitch max - 0.018 - - - - 0.059 - 0.059 - nom 0.22 0.015 0.2 1.58 2.15 0.065 0.056 0.065 0.056 - min - 0.012 - - - - 0.053 - 0.053 0.149 pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 58 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar [1] the x/y coordinates of the alignment mark loca tion represent the position of the ref point (see figure 41 ) with respect to the center (x/y = 0) of the chip; see figure 40 . [2] the x/y values of the dimensions represent the ext ensions of the alignment mark in direction of the coordinate axis (see figure 41 ). [1] pressure of diamond head: 10 g to 50 g. table 51. bump locations all x/y coordinates represent the position of the ce nter of each bump with respect to the center (x/y = 0) of the chip; see figure 40 . symbol bump coordinates ( ? m) x y v dd 1 714.4 911.7 osci 2 ? 714.4 988.3 osco 3 ? 714.4 707.3 v bat 4 ? 714.4 ? 199.3 v ss 5 ? 714.4 ? 459.1 n.c. 6 ? 714.4 ? 616.7 int2 7 ? 714.4 ? 895.4 clkout 8 714.4 ? 922.0 sda 9 714.4 ? 528.8 scl 10 714.4 ? 101.1 n.c. 11 714.4 607.6 int1 /clkout 12 714.4 763.2 table 52. alignment mark dimension and location coordinates x y location [1] 631.3 ? m 891.7 ? m dimension [2] 44.25 ? m 36.5 ? m fig 41. alignment mark table 53. gold bump hardness of pcf8523u gold bump type min max unit [1] soft gold bump 35 80 hv 013aaa318 ref y x pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 59 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 16. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling metal-oxide semiconductor (mos) devices ensure that all normal precautions are taken as described in jesd625-a , iec 61340-5 or equivalent standards. 17. packing information 17.1 tape and reel information fig 42. tape and reel details for pcf8523 table 54. carrier tape dimensions of pcf8523 symbol description value unit sot96-1 (so8) of pcf8523t a0 pocket width in x direction 6.30 to 6.65 mm b0 pocket width in y direction 5.40 mm k0 pocket depth 2.05 to 2.10 mm p1 pocket hole pitch 8.0 mm w tape width in y direction 12.0 mm sot909-1 (hvson8) of pcf8523tk a0 pocket width in x direction 4.25 to 4.30 mm b0 pocket width in y direction 4.25 to 4.30 mm k0 pocket depth 1.1 mm p1 pocket hole pitch 8.0 mm w tape width in y direction 12.0 mm 013aaa698 direction of feed top view 4.0 a0 p1 b0 w k0 ? 1.5 ? 1.5 original dimensions are in mm. figure not drawn to scale. pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 60 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 17.2 wafer and film frame carrier (ffc) information sot402-1 (tssop14) of pcf8523ts a0 pocket width in x direction 6.95 mm b0 pocket width in y direction 5.6 mm k0 pocket depth 1.6 mm p1 pocket hole pitch 8.0 mm w tape width in y direction 12.0 mm table 54. carrier tape dimensions of pcf8523 ?continued symbol description value unit (1) die marking code. seal ring plus gap to active circuit ~18 ? m. wafer thickness 200 ? m. pcf8523u: bad die are marked in wafer mapping. fig 43. pcf8523u wafer information 013aaa232 saw lane ~18 m 45 m 70 m ~18 m detail x 1.449 mm 1.492 mm 1 1 1 1 x straight edge of the wafer (1) pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 61 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar fig 44. film frame carrie r (ffc) (for pcf8523u) 013aaa351 2.6 mm 60.2 mm 63.5 mm ? 250 mm ? 296 mm 276 mm 276 mm 0.3 plastic frame plastic film straight edge of the wafer pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 62 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 18. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 18.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 18.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 18.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 63 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 18.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 45 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 5 5 and 56 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 45 . table 55. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 56. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 64 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 19. footprint information msl: moisture sensitivity level fig 45. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature fig 46. footprint information for reflow soldering of sot96-1 (so8) of pcf8523t sot096-1_fr occupied area solder lands dimensions in mm placement accuracy 0.25 1.30 0.60 (8) 1.27 (6) 4.00 6.60 5.50 7.00 pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 65 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar fig 47. footprint information for reflow soldering of sot402-1 (tssop14) of pcf8523ts dimensions in mm ay by d1 d2 gy hy p1 7.200 4.500 1.350 0.400 c 0.600 4.950 5.300 gx 7.450 sot402-1_fr hx 5.800 0.650 sot402-1 solder land occupied area footprint information for reflow soldering of tssop14 package ay by gy c hy hx gx p1 generic footprint pattern refer to the package outline drawing for actual layout p2 (0.125) (0.125) d1 d2 (4x) p2 0.750 pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 66 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 20. abbreviations table 57. abbreviations acronym description am ante meridiem bcd binary coded decimal cdm charged-device model cmos complementary metal-oxide semiconductor dc direct current ffc film frame carrier hbm human body model i 2 c inter-integrated circuit bus ic integrated circuit lsb least significant bit mcu microcontroller unit msb most significant bit msl moisture sensitivity level pcb printed-circuit board pm post meridiem por power-on reset rtc real-time clock scl serial clock line sda serial data line smd surface mount device sr slew rate pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 67 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 21. references [1] an10365 ? surface mount reflow soldering description [2] an10706 ? handling bare die [3] an10853 ? esd and emc sensitivity of ic [4] iec 60134 ? rating systems for electronic tu bes and valves and analogous semiconductor devices [5] iec 61340-5 ? protection of electronic devices from electrostatic phenomena [6] ipc/jedec j-std-020d ? moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices [7] jesd22-a114 ? electrostatic discharge (esd) sensitivity testing human body model (hbm) [8] jesd22-c101 ? field-induced charged-device model test method for electrostatic-discharge-withstand thresh olds of microelectronic components [9] jesd78 ? ic latch-up test [10] jesd625-a ? requirements for handling elec trostatic-discharge-sensitive (esds) devices [11] snv-fa-01-02 ? marking formats integrated circuits [12] um10204 ? i 2 c-bus specification and user manual [13] um10569 ? store and transport requirements pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 68 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 22. revision history table 58. revision history document id release date data sheet status change notice supersedes pcf8523 v.4 20120705 product data sheet - pcf8523 v.3 modifications: ? added section 4.1 , section 17.1 , section 8.8.3 , and section 19 ? added i 2 c read and write address to feature list ? fixed figure 33 ? fixed typos pcf8523 v.3 20110330 product data sheet - pcf8523 v.2 pcf8523 v.2 20110127 product data sheet - pcf8523 v.1 pcf8523 v.1 20101123 product data sheet - - pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 69 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 23. legal information 23.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 23.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 23.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification. pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 70 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully in demnifies nxp semi conductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive appl ications beyond nxp semiconductors? standard warranty and nxp semicond uctors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. bare die ? all die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the nxp semiconductors storage and transportation conditions. if there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. there are no post-packing tests performed on individual die or wafers. nxp semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. accordingly, nxp semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used. all die sales are conditioned upon and subject to the customer entering into a written die sale agreement with nxp semiconductors through its legal department. 23.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 24. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 71 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 25. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .2 table 2. ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3. pcf8523u wafer informati on . . . . . . . . . . . . . . .2 table 4. marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 5. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 table 6. registers overview . . . . . . . . . . . . . . . . . . . . . .7 table 7. control_1 - contro l and status register 1 (address 00h) bit description . . . . . . . . . . . . . . .9 table 8. control_2 - contro l and status register 2 (address 01h) bit description . . . . . . . . . . . . . .10 table 9. control_3 - contro l and status register 3 (address 02h) bit description . . . . . . . . . . . . . . 11 table 10. register reset values . . . . . . . . . . . . . . . . . . . .12 table 11. power management function control bits . . . . .15 table 12. seconds - seconds and clock integrity status register (address 03h) bit description . . . . . . . .20 table 13. seconds coded in bcd format . . . . . . . . . . .20 table 14. minutes - minutes register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .21 table 15. hours - hours register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .21 table 16. days - days register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .21 table 17. weekdays - weekdays register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .22 table 18. weekday assignments . . . . . . . . . . . . . . . . . . .22 table 19. months - months register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .22 table 20. month assignments in bcd format . . . . . . . . . .22 table 21. years - years register (09h) bit description . . . .23 table 22. minute_alarm - minute alarm register (address 0ah) bit description . . . . . . . . . . . . . .24 table 23. hour_alarm - hour alarm register (address 0bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .24 table 24. day_alarm - day alarm register (address 0ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .25 table 25. weekday_alarm - weekday alarm register (address 0dh) bit description . . . . . . . . . . . . . .25 table 26. flag location in register control_2 . . . . . . . . . .26 table 27. example to clear only af (bit 3). . . . . . . . . . . . 26 table 28. offset - offset register (address 0eh) bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 29. offset values . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 30. correction pulses for mode = 0 . . . . . . . . . . . 29 table 31. effect of clock correction for mode = 0. . . . . . 29 table 32. correction pulses for mode = 1 . . . . . . . . . . . 30 table 33. effect of clock corre ction for mode = 1 . . . . . 30 table 34. tmr_clkout_ctrl - timer and clkout control register (address 0fh) bit description . . . . . . . 32 table 35. clkout frequency selection . . . . . . . . . . . . . 33 table 36. tmr_a_freq_ctrl - timer a frequency control register (address 10h) bit description . . . . . . . 33 table 37. tmr_a_reg - timer a value register (address 11h) bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 38. tmr_b_freq_ctrl - timer b frequency control register (address 12h) bit description . . . . . . . 34 table 39. tmr_b_reg - timer b value register (address 13h) bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 40. programmable timer characteristics . . . . . . . . 35 table 41. first period delay for timer counter value n . . . 37 table 42. effect of bit sie on int1 and bit sf . . . . . . . . . 39 table 43. interrupt low pulse width for timer a. . . . . . . . . 40 table 44. interrupt low pulse width for timer b. . . . . . . . . 41 table 45. first increment of time circuits after stop release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 46. i 2 c slave address byte . . . . . . . . . . . . . . . . . . . 47 table 47. limiting values . . . . . . . . . . . . . . . . . . . . . . . . 49 table 48. static characteristics . . . . . . . . . . . . . . . . . . . . 50 table 49. i 2 c-bus interface timing . . . . . . . . . . . . . . . . . . 52 table 50. dimensions of pcf8523u . . . . . . . . . . . . . . . . 57 table 51. bump locations . . . . . . . . . . . . . . . . . . . . . . . . 58 table 52. alignment mark dimension and location . . . . . 58 table 53. gold bump hardness of pcf8523u. . . . . . . . . 58 table 54. carrier tape dimensions of pcf8523 . . . . . . . 59 table 55. snpb eutectic process (from j-std-020c) . . . 63 table 56. lead-free process (from j-std-020c) . . . . . . 63 table 57. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 58. revision history . . . . . . . . . . . . . . . . . . . . . . . . 68 pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 72 of 74 nxp semiconductors pcf8523 real-time clock (rtc) and calendar 26. figures fig 1. block diagram of pcf8523 . . . . . . . . . . . . . . . . . .3 fig 2. pin configuration for so8 (pcf8523t) . . . . . . . . .4 fig 3. pin configuration for hvson8 (pcf8523tk) . . . .4 fig 4. pin configuration fo r tssop14 (pcf8523ts). . . .4 fig 5. pin configuration for pcf8523u . . . . . . . . . . . . . .5 fig 6. auto-incrementing of the registers . . . . . . . . . . . . .7 fig 7. software reset command . . . . . . . . . . . . . . . . . . .12 fig 8. interrupt block diagram . . . . . . . . . . . . . . . . . . . .14 fig 9. battery switch-over behavior in standard mode and with bit bsie set logic 1 (enabled) . . . . . . . .17 fig 10. battery switch-over be havior in direct switching mode and with bit bsie set logic 1 (enabled) . . .18 fig 11. battery low detection behavior with bit blie set logic 1 (enabled) . . . . . . . . . . . . . . . . . . . . . .19 fig 12. os flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 fig 13. data flow diagram of the time function. . . . . . . . .23 fig 14. access time for read/write operations . . . . . . . . .23 fig 15. alarm function block diagram. . . . . . . . . . . . . . . .25 fig 16. alarm flag timing . . . . . . . . . . . . . . . . . . . . . . . . .26 fig 17. af timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 fig 18. offset calibration calculation workflow . . . . . . . . .31 fig 19. watchdog activates an interrupt when timed out .36 fig 20. general countdown timer behavior . . . . . . . . . . .37 fig 21. general countdown timer behavior . . . . . . . . . . .38 fig 22. example for second interrupt when tam = 1. . . .40 fig 23. example for second interrupt when tam = 0. . . .40 fig 24. example of shortening the int1 pulse by clearing the sf flag . . . . . . . . . . . . . . . . . . . . . . .41 fig 25. example of shortening the int1 pulse by clearing the ctaf flag . . . . . . . . . . . . . . . . . . . . .42 fig 26. stop bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 fig 27. stop bit release timing . . . . . . . . . . . . . . . . . . . .43 fig 28. bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 fig 29. definition of start and stop conditions. . . . . .45 fig 30. system configuration . . . . . . . . . . . . . . . . . . . . . .46 fig 31. acknowledgement on the i 2 c-bus . . . . . . . . . . . .46 fig 32. bus protocol for write mode . . . . . . . . . . . . . . . . .47 fig 33. bus protocol for read mode . . . . . . . . . . . . . . . . .47 fig 34. device diode protection diagram of pcf8523 . .48 fig 35. i 2 c-bus timing diagram; rise and fall times refer to 30 % and 70 % . . . . . . . . . . . . . . . . . . . . . . . .53 fig 36. application diagram . . . . . . . . . . . . . . . . . . . . . . .53 fig 37. package outline sot96-1 (so8) of pcf8523t. .54 fig 38. package outline sot909-1 (hvson8) of pcf8523tk . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 fig 39. package outline sot402-1 (tssop14) of pcf8523ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 fig 40. bare die outline of pcf8523 u . . . . . . . . . . . . . . .57 fig 41. alignment mark . . . . . . . . . . . . . . . . . . . . . . . . . .58 fig 42. tape and reel details for pcf8523 . . . . . . . . . . .59 fig 43. pcf8523u wafer information. . . . . . . . . . . . . . . .60 fig 44. film frame carrier (ffc) (for pcf8523u) . . . . .61 fig 45. temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 fig 46. footprint information for reflow soldering of sot96-1 (so8) of pcf8523t . . . . . . . . . . . . . . .64 fig 47. footprint information for reflow soldering of sot402-1 (tssop14) of pcf8523ts . . . . . . . . 65 pcf8523 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 4 ? 5 july 2012 73 of 74 continued >> nxp semiconductors pcf8523 real-time clock (rtc) and calendar 27. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 functional description . . . . . . . . . . . . . . . . . . . 6 8.1 registers overview . . . . . . . . . . . . . . . . . . . . . . 7 8.2 control and status registers . . . . . . . . . . . . . . . 9 8.2.1 register control_1 . . . . . . . . . . . . . . . . . . . . . . 9 8.2.2 register control_2 . . . . . . . . . . . . . . . . . . . . . 10 8.2.3 register control_3 . . . . . . . . . . . . . . . . . . . . . 11 8.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.4 interrupt function. . . . . . . . . . . . . . . . . . . . . . . 13 8.5 power management functions . . . . . . . . . . . . 15 8.5.1 standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 15 8.5.2 battery switch-over function . . . . . . . . . . . . . . 16 8.5.2.1 standard mode . . . . . . . . . . . . . . . . . . . . . . . . 17 8.5.2.2 direct switching mode . . . . . . . . . . . . . . . . . . 18 8.5.2.3 battery switch-over disabled, only one power supply (v dd ) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.5.3 battery low detection function. . . . . . . . . . . . . 18 8.6 time and date registers . . . . . . . . . . . . . . . . . 19 8.6.1 register seconds . . . . . . . . . . . . . . . . . . . . . . 20 8.6.1.1 oscillator stop flag . . . . . . . . . . . . . . . . . . . . 20 8.6.2 register minutes. . . . . . . . . . . . . . . . . . . . . . . 21 8.6.3 register hours . . . . . . . . . . . . . . . . . . . . . . . . 21 8.6.4 register days . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.6.5 register weekdays. . . . . . . . . . . . . . . . . . . . . 22 8.6.6 register months . . . . . . . . . . . . . . . . . . . . . . . 22 8.6.7 register years . . . . . . . . . . . . . . . . . . . . . . . . 23 8.6.8 data flow of the time function . . . . . . . . . . . . . 23 8.7 alarm registers . . . . . . . . . . . . . . . . . . . . . . . . 24 8.7.1 register minute_alarm . . . . . . . . . . . . . . . . . . 24 8.7.2 register hour_alarm . . . . . . . . . . . . . . . . . . . 24 8.7.3 register day_alarm . . . . . . . . . . . . . . . . . . . . 25 8.7.4 register weekday_alarm . . . . . . . . . . . . . . . . 25 8.7.5 alarm flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.7.6 alarm interrupts . . . . . . . . . . . . . . . . . . . . . . . 27 8.8 register offset . . . . . . . . . . . . . . . . . . . . . . . . 28 8.8.1 correction when mode = 0 . . . . . . . . . . . . . . 29 8.8.2 correction when mode = 1 . . . . . . . . . . . . . . 30 8.8.3 offset calibration workflow . . . . . . . . . . . . . . . 31 8.9 timer function . . . . . . . . . . . . . . . . . . . . . . . . 32 8.9.1 timer registers . . . . . . . . . . . . . . . . . . . . . . . . 32 8.9.1.1 register tmr_clkout_ctrl and clock output 32 8.9.1.2 clkout frequency selection . . . . . . . . . . . . 32 8.9.1.3 register tmr_a_freq_ctrl. . . . . . . . . . . . . . . . 33 8.9.1.4 register tmr_a_reg. . . . . . . . . . . . . . . . . . . . 34 8.9.1.5 register tmr_b_freq_ctrl. . . . . . . . . . . . . . . . 34 8.9.1.6 register tmr_b_reg . . . . . . . . . . . . . . . . . . . 34 8.9.1.7 programmable timer characteristics . . . . . . . 35 8.9.2 timer a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.9.2.1 watchdog timer function . . . . . . . . . . . . . . . . 35 8.9.2.2 countdown timer function . . . . . . . . . . . . . . . 36 8.9.3 timer b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.9.4 second interrupt timer . . . . . . . . . . . . . . . . . . 39 8.9.5 timer interrupt pulse . . . . . . . . . . . . . . . . . . . 40 8.10 stop bit function . . . . . . . . . . . . . . . . . . . . . . 43 8.11 i 2 c-bus interface . . . . . . . . . . . . . . . . . . . . . . 45 8.11.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.11.2 start and stop conditions. . . . . . . . . . . . . 45 8.11.3 system configuration . . . . . . . . . . . . . . . . . . . 45 8.11.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.11.5 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 46 9 internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 48 10 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 49 11 static characteristics . . . . . . . . . . . . . . . . . . . 50 12 dynamic characteristics. . . . . . . . . . . . . . . . . 52 13 application information . . . . . . . . . . . . . . . . . 53 14 package outline. . . . . . . . . . . . . . . . . . . . . . . . 54 15 bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 57 16 handling information . . . . . . . . . . . . . . . . . . . 59 17 packing information . . . . . . . . . . . . . . . . . . . . 59 17.1 tape and reel information . . . . . . . . . . . . . . . 59 17.2 wafer and film frame carrier (ffc) information . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 18 soldering of smd packages . . . . . . . . . . . . . . 62 18.1 introduction to soldering. . . . . . . . . . . . . . . . . 62 18.2 wave and reflow soldering. . . . . . . . . . . . . . . 62 18.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 62 18.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 63 19 footprint information . . . . . . . . . . . . . . . . . . . 64 20 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 66 21 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 22 revision history . . . . . . . . . . . . . . . . . . . . . . . 68 23 legal information . . . . . . . . . . . . . . . . . . . . . . 69 nxp semiconductors pcf8523 real-time clock (rtc) and calendar ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 5 july 2012 document identifier: pcf8523 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 23.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 69 23.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 23.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 23.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 70 24 contact information. . . . . . . . . . . . . . . . . . . . . 70 25 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 26 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 27 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 mouser electronics authorized distributor click to view pricing, inventory, delivery & lifecycle information: nxp: ? pcf8523t/1,118? pcf8523tk/1,118? pcf8523ts/1,112? pcf8523ts/1,118 |
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